Some personal minutes

Really only buzz words, but I hope the order of the talks is correct. If I missed, misunderstood, or mispelled anything, feel free to correct.

Wednesday, 18.7.2007

Meeting starts 16h (2h late), 22 people

Patricia Chomaz, GANIL outdated electronics must be replaced. SPEG/MUST: , VICBUS->VME, some to 50kHz, VAMOS/MAYA(Tanihata, TRIUMF), GASSIPLEX ASIC + CAEN CRAMS, 2.-3 kHz, MUST2, Si strips 3000-5000 channels, MATE ASIC, VAMOS+EXOGAM+Tiara+MUST2 Oct07-Apr08

Daniel Cano Ott CIEMAT (Madrid, could not come) : Neutron wall Ismael Martel shows slides. Flash ADC for DESPEC, n,γ separation, 12bit ADC, 500Mhz, FPGA+DSP, prototype board end 2008. Design not yet finished

Ignacio Duran Santiago : Calorimeter. showed DAQ-chain NIM-VME-MBS-GO4. STAR+TAQUILA. Question is TAQUILA future?

Haik Simon : Neutron wall (LAND, Taquila, TAC chips from Dresden), 10ps sigma. Needed: synchronize DAQ-systems by TDS, Add I2C, SAM-VME-MBS
Pollacco:Time distribution system should be general. R3B, SIDEREM
Proposed SiliconStrip-Detector demonstrator (self triggered, remote calibrated readout). Readout boards: ceramics (Kisselev) Beamtracking with diamonds
APV FE board M.Böhmer TUM (for CMS), readout board under dev.

Olof Tengblat CSIC Madrid : Calorimeter High energy branch of SFRS calorimeter around target before R3B.

Jean-Eric Ducret (Saclay) : TPC/GLAD

Philippe Legou : TPC detector construction, 4000 channels, 10kHz

Patricia Chomaz JRA01: ACTAR (new active target) Evaluate: GASSIPLEX, ALTRO (Alice TPC), T2K

Ian Lazarus : EXL Silicon Particle Array (ESPA) 500 kChannels.. ADC cards with PCIex, BUTIS time system
AGATA, LYCCA (calorimeter), AIDA (Implantation Array) Asic analog and digital output.
AGATA: 15 Crystals in 2008 (Legnaro), 45 2010 (Ganil), 180 GSI 2012
Puls shape analysis cuurently bottleneck. Global Trigger System slows down data rate for PSA. Digitizers in Production.

Ismael Martel : HYDE (low energy branch of FAIR) Very exotic nuclei. Project of Huelva. Demonstrator 2010

20h Session must close

Thursday, 19.7.2007, 9h
Haik Simon : ELISE

Giacomo Poggi INFN : FAZIA, FEE, JRA. SPIRAL2, LNL/SPES, FAIR. Pulse shape analysis with Si-Detectors. Simulations, algorithms. Nuclear Crystallography

Emanual Pollacco CEA Saclay: GASPARD @ SPIRAL2 (2011-2015) MUST2-Detector (double sided strip detector DSSD) + tracking for beam position & reaction time stamp. Particle+ γ detection

Laurant Olivier GANIL : EXOGAM2 FADCs, self triggered, GE, ADONIS, VXE->ATCA,cPCI. 60 MB/s, CENTRUM (VXI only) time, Compared different FEE solutions. Propose ATCA because of AGATA.

Ivan Mukha Sevilla : beam tracking

11.30h Resume so far
Emanual Pollacco: Synergy group Networking
  • Survay
  • Forum for NP instrumentation
  • Forum technical-physics
  • Identification of key fields
  • Identification of controls tasks (testing, setup, calibration)
  • Tools to handle complex detector systems
  • Engineers-physicists
  • Generic infrastructures?
  • Generalized cards?
Alternativs to JRA?

ASICs 15h
Mark Prydderch RAL . RAL joined with Daresbury to Scientific and Technical F Council
CMS: Si strips, APV25 ASIC for readout, ILC, INMAPS, AIDA, XFEL, CMS upgrade

Eric Delangne CEA :MUST2, Mimosa8, replace GASSIPOLEX for COMPASS by APV25 based readout card (Si-strip).

Alberto Pullia Univ.Milano/INFN AGATA preamps.
Some discussion about configurable ASICS

FEE boards 17h
Frederic Drouillole CEA ILC, COMPASS, CMS, VME board with 4 ADC. Configuration from DB KM3net (see RT07), XML and OO style file format.

R.G.Carvajal Univ.Huelva ADC flash 350nm 500MHz, 130nm 1GHz, 6 bits . Standard 1mW per 10MHz

Raul Jimenez-Naharro Univ.Huelva

Discussion FEE
What is the range of requirements? Is formfactor a concern?

David Etasse CAEN : FASTER for FAZIA. Use cheap FPGA and Gigabit Ethernet connection to PC. Use Altera with softprocessor NiosII (80MHz). TCP stack expensive. Therefore write own. Achieved 1MByte/s. with scatter gather hop to get 5 Mbyte/s. Too slow. develop raw ethernet protocol LPC replacing TCP/IP gains >100Mbyte/s. 2000 cells. Digitizer 500MHz@12bits in FPGA.

Peter Zumbruch (GSI): EPICS

Hans Essel GSI : DABC

Bruno Raine : GANIL, Narval

Brief discussion, no result. Narval used by AGATA for political reasons. Nobody happy with choice of ADA

Friday, 20.7.2007, 9h
Matjaz Vencelj, Lucia-Ana Popescu KVI : Controls and Pulse shape analysis. Testboard HADES TRD2, GRIDCC, MonALISA, EPICS, digital PSA. Flash data is processed in FPGA. Samples of data are analyzed by softcore CPU optimizing parameters for the fast data prozessing. Shape analysis for position and integral. Separate n and γ.

Juan-Luis Flores (Ismael Martel) Huelva : PID by PSA neural networks. Very good results. Question of learning. 2 neuron layers, 20 neurons

JRA+Network 10.30h
Call for. 39 responses. Cut from 10 M€ to 5M€
Helsinki 17-20th Sept.: presentation and choice of projects
Feb.2008 : Comity to deliver full proposal suite

Ian: Universal system not possible, rather selection of modules like functional blocks.
JRA deliverable is a pilot system, i.e. FEE board with building blocks.
  • mezzanine or FPGA-IP for GTS
  • TOF circuits
  • Preamps
  • Digitizers 2GHz 12bit
  • Control hook on board
Define standards for interfaces Design the functional blocks ASIC costs 250k€ + 6MY, cards: 30k€+1.5, FEE card 5k€, software 2MY, cables 40k€, network 60k€, DAQ software 6MY, travel 100k€
Total 2 M€, 1.4 of it manpower.
Vic: DABC and NARVAL. Labs have to guarantee experiment running. Can DABC API implemented in NARVAL also? Essel: hard to say, probably not directly, reusable code possible. GRIDCC used at AGATA, but still to investigate.
Essel: System integration, DAQ not only ASICS and FEE.

-- HansEssel - 02 Aug 2007
Topic revision: r4 - 2007-08-28, HansEssel
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